Technologies for structured database query for finding unique element values

ABSTRACT

Technologies for determining unique values include a computing device that further includes one or more accelerator devices. Each accelerator device is to receive input data and query configuration data, the input data including a packed array of unsigned integers of column data from a database and the query configuration data including an element width of the input data, and generate, in response to receiving the query configuration data, a bit-map output table based on the query configuration data, generate a write request for each element of the input data to set a corresponding bit-map output bit of the bit-map output table which corresponds to an element value of the corresponding element. Subsequently, the accelerator device is further to set the corresponding bit-map output bit to indicate a presence of the corresponding element and output the bit-map output table indicative of unique elements that are present in the input data.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of Indian Provisional PatentApplication No. 201741030632, filed Aug. 30, 2017, and U.S. ProvisionalPatent Application No. 62/584,401, filed Nov. 10, 2017.

BACKGROUND

Unique values queries are typically performed by processors of acomputing device to determine a presence of distinct or unique values indatabase. The unique values queries are often used to filter largedatabase columns to obtain unique element values that are present in thedatabase. However, processor-based implementations may requireconsumption of large amounts of power and other resources due to theamount of data that is required to be read into the processors.

Modern computing devices may include general-purpose processor cores aswell as a variety of hardware accelerators for performing specializedtasks. Certain computing devices may include one or more acceleratorsembodied as field-programmable gate arrays (FPGAs), which may includeprogrammable digital logic resources that may be configured by the enduser or system integrator.

BRIEF DESCRIPTION OF THE DRAWINGS

The concepts described herein are illustrated by way of example and notby way of limitation in the accompanying figures. For simplicity andclarity of illustration, elements illustrated in the figures are notnecessarily drawn to scale. Where considered appropriate, referencelabels have been repeated among the figures to indicate corresponding oranalogous elements.

FIG. 1 is a diagram of a conceptual overview of a data center in whichone or more techniques described herein may be implemented according tovarious embodiments;

FIG. 2 is a diagram of an example embodiment of a logical configurationof a rack of the data center of FIG. 1;

FIG. 3 is a diagram of an example embodiment of another data center inwhich one or more techniques described herein may be implementedaccording to various embodiments;

FIG. 4 is a diagram of another example embodiment of a data center inwhich one or more techniques described herein may be implementedaccording to various embodiments;

FIG. 5 is a diagram of a connectivity scheme representative oflink-layer connectivity that may be established among various sleds ofthe data centers of FIGS. 1, 3, and 4;

FIG. 6 is a diagram of a rack architecture that may be representative ofan architecture of any particular one of the racks depicted in FIGS. 1-4according to some embodiments;

FIG. 7 is a diagram of an example embodiment of a sled that may be usedwith the rack architecture of FIG. 6;

FIG. 8 is a diagram of an example embodiment of a rack architecture toprovide support for sleds featuring expansion capabilities;

FIG. 9 is a diagram of an example embodiment of a rack implementedaccording to the rack architecture of FIG. 8;

FIG. 10 is a diagram of an example embodiment of a sled designed for usein conjunction with the rack of FIG. 9;

FIG. 11 is a diagram of an example embodiment of a data center in whichone or more techniques described herein may be implemented according tovarious embodiments;

FIG. 12 is a simplified block diagram of at least one embodiment of acomputing device for determining unique values;

FIG. 13 is a simplified block diagram of at least one embodiment of anenvironment that may be established by an accelerator of the computingdevice of FIG. 12; and

FIGS. 14 and 15 are a simplified flow diagram of at least one embodimentof a method for determining unique values that may be executed by theaccelerator of FIGS. 12 and 13.

DETAILED DESCRIPTION OF THE DRAWINGS

While the concepts of the present disclosure are susceptible to variousmodifications and alternative forms, specific embodiments thereof havebeen shown by way of example in the drawings and will be describedherein in detail. It should be understood, however, that there is nointent to limit the concepts of the present disclosure to the particularforms disclosed, but on the contrary, the intention is to cover allmodifications, equivalents, and alternatives consistent with the presentdisclosure and the appended claims.

References in the specification to “one embodiment,” “an embodiment,”“an illustrative embodiment,” etc., indicate that the embodimentdescribed may include a particular feature, structure, orcharacteristic, but every embodiment may or may not necessarily includethat particular feature, structure, or characteristic. Moreover, suchphrases are not necessarily referring to the same embodiment. Further,when a particular feature, structure, or characteristic is described inconnection with an embodiment, it is submitted that it is within theknowledge of one skilled in the art to effect such feature, structure,or characteristic in connection with other embodiments whether or notexplicitly described. Additionally, it should be appreciated that itemsincluded in a list in the form of “at least one A, B, and C” can mean(A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).Similarly, items listed in the form of “at least one of A, B, or C” canmean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).

The disclosed embodiments may be implemented, in some cases, inhardware, firmware, software, or any combination thereof. The disclosedembodiments may also be implemented as instructions carried by or storedon a transitory or non-transitory machine-readable (e.g.,computer-readable) storage medium, which may be read and executed by oneor more processors. A machine-readable storage medium may be embodied asany storage device, mechanism, or other physical structure for storingor transmitting information in a form readable by a machine (e.g., avolatile or non-volatile memory, a media disc, or other media device).

In the drawings, some structural or method features may be shown inspecific arrangements and/or orderings. However, it should beappreciated that such specific arrangements and/or orderings may not berequired. Rather, in some embodiments, such features may be arranged ina different manner and/or order than shown in the illustrative figures.Additionally, the inclusion of a structural or method feature in aparticular figure is not meant to imply that such feature is required inall embodiments and, in some embodiments, may not be included or may becombined with other features.

FIG. 1 illustrates a conceptual overview of a data center 100 that maygenerally be representative of a data center or other type of computingnetwork in/for which one or more techniques described herein may beimplemented according to various embodiments. As shown in FIG. 1, datacenter 100 may generally contain a plurality of racks, each of which mayhouse computing equipment comprising a respective set of physicalresources. In the particular non-limiting example depicted in FIG. 1,data center 100 contains four racks 102A to 102D, which house computingequipment comprising respective sets of physical resources (PCRs) 105Ato 105D. According to this example, a collective set of physicalresources 106 of data center 100 includes the various sets of physicalresources 105A to 105D that are distributed among racks 102A to 102D.Physical resources 106 may include resources of multiple types, suchas—for example—processors, co-processors, accelerators, fieldprogrammable gate arrays (FPGAs), memory, and storage. The embodimentsare not limited to these examples.

The illustrative data center 100 differs from typical data centers inmany ways. For example, in the illustrative embodiment, the circuitboards (“sleds”) on which components such as CPUs, memory, and othercomponents are placed for increased thermal performance In particular,in the illustrative embodiment, the sleds are shallower than typicalboards. In other words, the sleds are shorter from the front to theback, where cooling fans are located. This decreases the length of thepath that air must to travel across the components on the board.Further, the components on the sled are spaced further apart than intypical circuit boards, and the components are arranged to reduce oreliminate shadowing (i.e., one component in the air flow path of anothercomponent). In the illustrative embodiment, processing components suchas the processors are located on a top side of a sled while near memory,such as DIMMs, are located on a bottom side of the sled. As a result ofthe enhanced airflow provided by this design, the components may operateat higher frequencies and power levels than in typical systems, therebyincreasing performance Furthermore, the sleds are configured to blindlymate with power and data communication cables in each rack 102A, 102B,102C, 102D, enhancing their ability to be quickly removed, upgraded,reinstalled, and/or replaced. Similarly, individual components locatedon the sleds, such as processors, accelerators, memory, and data storagedrives, are configured to be easily upgraded due to their increasedspacing from each other. In the illustrative embodiment, the componentsadditionally include hardware attestation features to prove theirauthenticity.

Furthermore, in the illustrative embodiment, the data center 100utilizes a single network architecture (“fabric”) that supports multipleother network architectures including Ethernet and Omni-Path. The sleds,in the illustrative embodiment, are coupled to switches via opticalfibers, which provide higher bandwidth and lower latency than typicaltwisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.).Due to the high bandwidth, low latency interconnections and networkarchitecture, the data center 100 may, in use, pool resources, such asmemory, accelerators (e.g., graphics accelerators, FPGAs, ASICs, etc.),and data storage drives that are physically disaggregated, and providethem to compute resources (e.g., processors) on an as needed basis,enabling the compute resources to access the pooled resources as if theywere local. The illustrative data center 100 additionally receivesutilization information for the various resources, predicts resourceutilization for different types of workloads based on past resourceutilization, and dynamically reallocates the resources based on thisinformation.

The racks 102A, 102B, 102C, 102D of the data center 100 may includephysical design features that facilitate the automation of a variety oftypes of maintenance tasks. For example, data center 100 may beimplemented using racks that are designed to be robotically-accessed,and to accept and house robotically-manipulatable resource sleds.Furthermore, in the illustrative embodiment, the racks 102A, 102B, 102C,102D include integrated power sources that receive a greater voltagethan is typical for power sources. The increased voltage enables thepower sources to provide additional power to the components on eachsled, enabling the components to operate at higher than typicalfrequencies.

FIG. 2 illustrates an exemplary logical configuration of a rack 202 ofthe data center 100. As shown in FIG. 2, rack 202 may generally house aplurality of sleds, each of which may comprise a respective set ofphysical resources. In the particular non-limiting example depicted inFIG. 2, rack 202 houses sleds 204-1 to 204-4 comprising respective setsof physical resources 205-1 to 205-4, each of which constitutes aportion of the collective set of physical resources 206 comprised inrack 202. With respect to FIG. 1, if rack 202 is representative of—forexample—rack 102A, then physical resources 206 may correspond to thephysical resources 105A comprised in rack 102A. In the context of thisexample, physical resources 105A may thus be made up of the respectivesets of physical resources, including physical storage resources 205-1,physical accelerator resources 205-2, physical memory resources 205-3,and physical compute resources 205-4 comprised in the sleds 204-1 to204-4 of rack 202. The embodiments are not limited to this example. Eachsled may contain a pool of each of the various types of physicalresources (e.g., compute, memory, accelerator, storage). By havingrobotically accessible and robotically manipulatable sleds comprisingdisaggregated resources, each type of resource can be upgradedindependently of each other and at their own optimized refresh rate.

FIG. 3 illustrates an example of a data center 300 that may generally berepresentative of one in/for which one or more techniques describedherein may be implemented according to various embodiments. In theparticular non-limiting example depicted in FIG. 3, data center 300comprises racks 302-1 to 302-32. In various embodiments, the racks ofdata center 300 may be arranged in such fashion as to define and/oraccommodate various access pathways. For example, as shown in FIG. 3,the racks of data center 300 may be arranged in such fashion as todefine and/or accommodate access pathways 311A, 311B, 311C, and 311D. Insome embodiments, the presence of such access pathways may generallyenable automated maintenance equipment, such as robotic maintenanceequipment, to physically access the computing equipment housed in thevarious racks of data center 300 and perform automated maintenance tasks(e.g., replace a failed sled, upgrade a sled). In various embodiments,the dimensions of access pathways 311A, 311B, 311C, and 311D, thedimensions of racks 302-1 to 302-32, and/or one or more other aspects ofthe physical layout of data center 300 may be selected to facilitatesuch automated operations. The embodiments are not limited in thiscontext.

FIG. 4 illustrates an example of a data center 400 that may generally berepresentative of one in/for which one or more techniques describedherein may be implemented according to various embodiments. As shown inFIG. 4, data center 400 may feature an optical fabric 412. Opticalfabric 412 may generally comprise a combination of optical signalingmedia (such as optical cabling) and optical switching infrastructure viawhich any particular sled in data center 400 can send signals to (andreceive signals from) each of the other sleds in data center 400. Thesignaling connectivity that optical fabric 412 provides to any givensled may include connectivity both to other sleds in a same rack andsleds in other racks. In the particular non-limiting example depicted inFIG. 4, data center 400 includes four racks 402A to 402D. Racks 402A to402D house respective pairs of sleds 404A-1 and 404A-2, 404B-1 and404B-2, 404C-1 and 404C-2, and 404D-1 and 404D-2. Thus, in this example,data center 400 comprises a total of eight sleds. Via optical fabric412, each such sled may possess signaling connectivity with each of theseven other sleds in data center 400. For example, via optical fabric412, sled 404A-1 in rack 402A may possess signaling connectivity withsled 404A-2 in rack 402A, as well as the six other sleds 404B-1, 404B-2,404C-1, 404C-2, 404D-1, and 404D-2 that are distributed among the otherracks 402B, 402C, and 402D of data center 400. The embodiments are notlimited to this example.

FIG. 5 illustrates an overview of a connectivity scheme 500 that maygenerally be representative of link-layer connectivity that may beestablished in some embodiments among the various sleds of a datacenter, such as any of example data centers 100, 300, and 400 of FIGS.1, 3, and 4. Connectivity scheme 500 may be implemented using an opticalfabric that features a dual-mode optical switching infrastructure 514.Dual-mode optical switching infrastructure 514 may generally comprise aswitching infrastructure that is capable of receiving communicationsaccording to multiple link-layer protocols via a same unified set ofoptical signaling media, and properly switching such communications. Invarious embodiments, dual-mode optical switching infrastructure 514 maybe implemented using one or more dual-mode optical switches 515. Invarious embodiments, dual-mode optical switches 515 may generallycomprise high-radix switches. In some embodiments, dual-mode opticalswitches 515 may comprise multi-ply switches, such as four-ply switches.In various embodiments, dual-mode optical switches 515 may featureintegrated silicon photonics that enable them to switch communicationswith significantly reduced latency in comparison to conventionalswitching devices. In some embodiments, dual-mode optical switches 515may constitute leaf switches 530 in a leaf-spine architectureadditionally including one or more dual-mode optical spine switches 520.

In various embodiments, dual-mode optical switches may be capable ofreceiving both Ethernet protocol communications carrying InternetProtocol (IP packets) and communications according to a second,high-performance computing (HPC) link-layer protocol (e.g., Intel'sOmni-Path Architecture's, InfiniBand™) via optical signaling media of anoptical fabric. As reflected in FIG. 5, with respect to any particularpair of sleds 504A and 504B possessing optical signaling connectivity tothe optical fabric, connectivity scheme 500 may thus provide support forlink-layer connectivity via both Ethernet links and HPC links. Thus,both Ethernet and HPC communications can be supported by a singlehigh-bandwidth, low-latency switch fabric. The embodiments are notlimited to this example.

FIG. 6 illustrates a general overview of a rack architecture 600 thatmay be representative of an architecture of any particular one of theracks depicted in FIGS. 1 to 4 according to some embodiments. Asreflected in FIG. 6, rack architecture 600 may generally feature aplurality of sled spaces into which sleds may be inserted, each of whichmay be robotically-accessible via a rack access region 601. In theparticular non-limiting example depicted in FIG. 6, rack architecture600 features five sled spaces 603-1 to 603-5. Sled spaces 603-1 to 603-5feature respective multi-purpose connector modules (MPCMs) 616-1 to616-5.

FIG. 7 illustrates an example of a sled 704 that may be representativeof a sled of such a type. As shown in FIG. 7, sled 704 may comprise aset of physical resources 705, as well as an MPCM 716 designed to couplewith a counterpart MPCM when sled 704 is inserted into a sled space suchas any of sled spaces 603-1 to 603-5 of FIG. 6. Sled 704 may alsofeature an expansion connector 717. Expansion connector 717 maygenerally comprise a socket, slot, or other type of connection elementthat is capable of accepting one or more types of expansion modules,such as an expansion sled 718. By coupling with a counterpart connectoron expansion sled 718, expansion connector 717 may provide physicalresources 705 with access to supplemental computing resources 705Bresiding on expansion sled 718. The embodiments are not limited in thiscontext.

FIG. 8 illustrates an example of a rack architecture 800 that may berepresentative of a rack architecture that may be implemented in orderto provide support for sleds featuring expansion capabilities, such assled 704 of FIG. 7. In the particular non-limiting example depicted inFIG. 8, rack architecture 800 includes seven sled spaces 803-1 to 803-7,which feature respective MPCMs 816-1 to 816-7. Sled spaces 803-1 to803-7 include respective primary regions 803-1A to 803-7A and respectiveexpansion regions 803-1B to 803-7B. With respect to each such sledspace, when the corresponding MPCM is coupled with a counterpart MPCM ofan inserted sled, the primary region may generally constitute a regionof the sled space that physically accommodates the inserted sled. Theexpansion region may generally constitute a region of the sled spacethat can physically accommodate an expansion module, such as expansionsled 718 of FIG. 7, in the event that the inserted sled is configuredwith such a module.

FIG. 9 illustrates an example of a rack 902 that may be representativeof a rack implemented according to rack architecture 800 of FIG. 8according to some embodiments. In the particular non-limiting exampledepicted in FIG. 9, rack 902 features seven sled spaces 903-1 to 903-7,which include respective primary regions 903-1A to 903-7A and respectiveexpansion regions 903-1B to 903-7B. In various embodiments, temperaturecontrol in rack 902 may be implemented using an air cooling system. Forexample, as reflected in FIG. 9, rack 902 may feature a plurality offans 921 that are generally arranged to provide air cooling within thevarious sled spaces 903-1 to 903-7. In some embodiments, the height ofthe sled space is greater than the conventional “1 U” server height. Insuch embodiments, fans 921 may generally comprise relatively slow, largediameter cooling fans as compared to fans used in conventional rackconfigurations. Running larger diameter cooling fans at lower speeds mayincrease fan lifetime relative to smaller diameter cooling fans runningat higher speeds while still providing the same amount of cooling. Thesleds are physically shallower than conventional rack dimensions.Further, components are arranged on each sled to reduce thermalshadowing (i.e., not arranged serially in the direction of air flow). Asa result, the wider, shallower sleds allow for an increase in deviceperformance because the devices can be operated at a higher thermalenvelope (e.g., 250 W) due to improved cooling (i.e., no thermalshadowing, more space between devices, more room for larger heat sinks,etc.).

MPCMs 916-1 to 916-7 may be configured to provide inserted sleds withaccess to power sourced by respective power modules 920-1 to 920-7, eachof which may draw power from an external power source 919. In variousembodiments, external power source 919 may deliver alternating current(AC) power to rack 902, and power modules 920-1 to 920-7 may beconfigured to convert such AC power to direct current (DC) power to besourced to inserted sleds. In some embodiments, for example, powermodules 920-1 to 920-7 may be configured to convert 277-volt AC powerinto 12-volt DC power for provision to inserted sleds via respectiveMPCMs 916-1 to 916-7. The embodiments are not limited to this example.

MPCMs 916-1 to 916-7 may also be arranged to provide inserted sleds withoptical signaling connectivity to a dual-mode optical switchinginfrastructure 914, which may be the same as—or similar to—dual-modeoptical switching infrastructure 514 of FIG. 5. In various embodiments,optical connectors contained in MPCMs 916-1 to 916-7 may be designed tocouple with counterpart optical connectors contained in MPCMs ofinserted sleds to provide such sleds with optical signaling connectivityto dual-mode optical switching infrastructure 914 via respective lengthsof optical cabling 922-1 to 922-7. In some embodiments, each such lengthof optical cabling may extend from its corresponding MPCM to an opticalinterconnect loom 923 that is external to the sled spaces of rack 902.In various embodiments, optical interconnect loom 923 may be arranged topass through a support post or other type of load-bearing element ofrack 902. The embodiments are not limited in this context. Becauseinserted sleds connect to an optical switching infrastructure via MPCMs,the resources typically spent in manually configuring the rack cablingto accommodate a newly inserted sled can be saved.

FIG. 10 illustrates an example of a sled 1004 that may be representativeof a sled designed for use in conjunction with rack 902 of FIG. 9according to some embodiments. Sled 1004 may feature an MPCM 1016 thatcomprises an optical connector 1016A and a power connector 1016B, andthat is designed to couple with a counterpart MPCM of a sled space inconjunction with insertion of MPCM 1016 into that sled space. CouplingMPCM 1016 with such a counterpart MPCM may cause power connector 1016 tocouple with a power connector comprised in the counterpart MPCM. Thismay generally enable physical resources 1005 of sled 1004 to sourcepower from an external source, via power connector 1016 and powertransmission media 1024 that conductively couples power connector 1016to physical resources 1005.

Sled 1004 may also include dual-mode optical network interface circuitry1026. Dual-mode optical network interface circuitry 1026 may generallycomprise circuitry that is capable of communicating over opticalsignaling media according to each of multiple link-layer protocolssupported by dual-mode optical switching infrastructure 914 of FIG. 9.In some embodiments, dual-mode optical network interface circuitry 1026may be capable both of Ethernet protocol communications and ofcommunications according to a second, high-performance protocol. Invarious embodiments, dual-mode optical network interface circuitry 1026may include one or more optical transceiver modules 1027, each of whichmay be capable of transmitting and receiving optical signals over eachof one or more optical channels. The embodiments are not limited in thiscontext.

Coupling MPCM 1016 with a counterpart MPCM of a sled space in a givenrack may cause optical connector 1016A to couple with an opticalconnector comprised in the counterpart MPCM. This may generallyestablish optical connectivity between optical cabling of the sled anddual-mode optical network interface circuitry 1026, via each of a set ofoptical channels 1025. Dual-mode optical network interface circuitry1026 may communicate with the physical resources 1005 of sled 1004 viaelectrical signaling media 1028. In addition to the dimensions of thesleds and arrangement of components on the sleds to provide improvedcooling and enable operation at a relatively higher thermal envelope(e.g., 250 W), as described above with reference to FIG. 9, in someembodiments, a sled may include one or more additional features tofacilitate air cooling, such as a heatpipe and/or heat sinks arranged todissipate heat generated by physical resources 1005. It is worthy ofnote that although the example sled 1004 depicted in FIG. 10 does notfeature an expansion connector, any given sled that features the designelements of sled 1004 may also feature an expansion connector accordingto some embodiments. The embodiments are not limited in this context.

FIG. 11 illustrates an example of a data center 1100 that may generallybe representative of one in/for which one or more techniques describedherein may be implemented according to various embodiments. As reflectedin FIG. 11, a physical infrastructure management framework 1150A may beimplemented to facilitate management of a physical infrastructure 1100Aof data center 1100. In various embodiments, one function of physicalinfrastructure management framework 1150A may be to manage automatedmaintenance functions within data center 1100, such as the use ofrobotic maintenance equipment to service computing equipment withinphysical infrastructure 1100A. In some embodiments, physicalinfrastructure 1100A may feature an advanced telemetry system thatperforms telemetry reporting that is sufficiently robust to supportremote automated management of physical infrastructure 1100A. In variousembodiments, telemetry information provided by such an advancedtelemetry system may support features such as failureprediction/prevention capabilities and capacity planning capabilities.In some embodiments, physical infrastructure management framework 1150Amay also be configured to manage authentication of physicalinfrastructure components using hardware attestation techniques. Forexample, robots may verify the authenticity of components beforeinstallation by analyzing information collected from a radio frequencyidentification (RFID) tag associated with each component to beinstalled. The embodiments are not limited in this context.

As shown in FIG. 11, the physical infrastructure 1100A of data center1100 may comprise an optical fabric 1112, which may include a dual-modeoptical switching infrastructure 1114. Optical fabric 1112 and dual-modeoptical switching infrastructure 1114 may be the same as—or similarto—optical fabric 412 of FIG. 4 and dual-mode optical switchinginfrastructure 514 of FIG. 5, respectively, and may providehigh-bandwidth, low-latency, multi-protocol connectivity among sleds ofdata center 1100. As discussed above, with reference to FIG. 1, invarious embodiments, the availability of such connectivity may make itfeasible to disaggregate and dynamically pool resources such asaccelerators, memory, and storage. In some embodiments, for example, oneor more pooled accelerator sleds 1130 may be included among the physicalinfrastructure 1100A of data center 1100, each of which may comprise apool of accelerator resources—such as co-processors and/or FPGAs, forexample—that is globally accessible to other sleds via optical fabric1112 and dual-mode optical switching infrastructure 1114.

In another example, in various embodiments, one or more pooled storagesleds 1132 may be included among the physical infrastructure 1100A ofdata center 1100, each of which may comprise a pool of storage resourcesthat is globally accessible to other sleds via optical fabric 1112 anddual-mode optical switching infrastructure 1114. In some embodiments,such pooled storage sleds 1132 may comprise pools of solid-state storagedevices such as solid-state drives (SSDs). In various embodiments, oneor more high-performance processing sleds 1134 may be included among thephysical infrastructure 1100A of data center 1100. In some embodiments,high-performance processing sleds 1134 may comprise pools ofhigh-performance processors, as well as cooling features that enhanceair cooling to yield a higher thermal envelope of up to 250 W or more.In various embodiments, any given high-performance processing sled 1134may feature an expansion connector 1117 that can accept a far memoryexpansion sled, such that the far memory that is locally available tothat high-performance processing sled 1134 is disaggregated from theprocessors and near memory comprised on that sled. In some embodiments,such a high-performance processing sled 1134 may be configured with farmemory using an expansion sled that comprises low-latency SSD storage.The optical infrastructure allows for compute resources on one sled toutilize remote accelerator/FPGA, memory, and/or SSD resources that aredisaggregated on a sled located on the same rack or any other rack inthe data center. The remote resources can be located one switch jumpaway or two-switch jumps away in the spine-leaf network architecturedescribed above with reference to FIG. 5. The embodiments are notlimited in this context.

In various embodiments, one or more layers of abstraction may be appliedto the physical resources of physical infrastructure 1100A in order todefine a virtual infrastructure, such as a software-definedinfrastructure 1100B. In some embodiments, virtual computing resources1136 of software-defined infrastructure 1100B may be allocated tosupport the provision of cloud services 1140. In various embodiments,particular sets of virtual computing resources 1136 may be grouped forprovision to cloud services 1140 in the form of software-definedinfrastructure (SDI) services 1138. Examples of cloud services 1140 mayinclude—without limitation—software as a service (SaaS) services 1142,platform as a service (PaaS) services 1144, and infrastructure as aservice (IaaS) services 1146.

In some embodiments, management of software-defined infrastructure 1100Bmay be conducted using a virtual infrastructure management framework1150B. In various embodiments, virtual infrastructure managementframework 1150B may be designed to implement workload fingerprintingtechniques and/or machine-learning techniques in conjunction withmanaging allocation of virtual computing resources 1136 and/or SDIservices 1138 to cloud services 1140. In some embodiments, virtualinfrastructure management framework 1150B may use/consult telemetry datain conjunction with performing such resource allocation. In variousembodiments, an application/service management framework 1150C may beimplemented in order to provide QoS management capabilities for cloudservices 1140. The embodiments are not limited in this context.

Referring now to FIG. 12, an illustrative system 1200 for determiningunique values, which may be implemented in accordance with the datacenters 100, 300, 400, 1100 described above with reference to FIGS. 1,3, 4, and 11, is shown. The illustrative system 1200 includes a computedevice 1202 that includes an accelerator 1204, a memory 1206, one ormore processors 1208, and one or more storage devices 1210. In use, asdescribed further below, the accelerator 1204 may filter a database todetermine unique values. In the illustrative embodiment, the accelerator1204 may receive input data, which is a packed array of unsignedintegers of column data from the database, to determine unique elementvalues of the input data. To do so, the accelerator 1204 may construct abit-map output table configured to store bit-map output bits based onquery configuration data received from a processor 1208, which includesa number of elements and an element width (N) of the input data and ahash width (K). It should be appreciated that the hash width (K) is lessthan or equal to the element width (N). Accordingly, the bit-map outputtable is sized to store 2^(K) number of bit-map output bits, eachbit-map output bit corresponds to a unique element value of the inputdata or a unique hash value that may be generated from the input data.In the illustrative embodiment, the accelerator 1240 may construct adifferent type of bit-map output tables on the accelerator 1240 based onthe hash width (K). For example, if the hash width (K) is less than 8bits, the accelerator 1240 may construct a small bit-map output tablewith multiple write ports (e.g., muxes) to provide multiple writes percycle. Alternatively, if the hash width (K) is greater than 8 bits, theaccelerator 1240 may construct a large bit-map output table. Theaccelerator 1204 may configure the large bit-map output table to storeduplicate copies of the bit-map output bits to support parallelaccesses, including parallel writes during input data processing intothe large bit-map output table and parallel reads during read outprocessing of the large bit-map output table.

Subsequently, the accelerator 1204 may generate a write request for eachelement to access the corresponding bit-map output table to set abit-map output bit that corresponds to the element value of thecorresponding element. To do so, the accelerator 1204 may adjust theelement width (N) of the input data by pre-processing the packed bitvector of column data. The pre-processing of the input data may supportunique values queries on any bit-width of elements of the database basedon a data path width of the accelerator 1240 and may also ensure that alargest number of elements are processed in each cycle. Since the inputdata is pre-processed and aligned with the bit-map output table, theaccelerator 1204 may use a corresponding element value of each elementas a write request address to issue the write request to thecorresponding bit-map output bit. Alternatively, if the element width(N) is different than the hash width (K), the accelerator 1204 mayperform the hash function on each element value to generate a hash valuethat is to be used as a write request address to access the bit-mapoutput table to set the corresponding bit-map output bit. After multiplepasses to process all elements of the input data, the accelerator 1204may output the bit-map output table that includes 2^(K) bit-map outputbits, where each set bit-map output bit indicates a presence of acorresponding unique element value or hash value. The accelerator 1204may then transfer the bit-map output table to the memory 1206 of thecompute device 1202 for further analysis or processing by one or moreprocessors 1208. By performing the unique values queries on the hardwareaccelerator 1204 instead of the processor 1208, the system 1200 mayincrease performance and power efficiency by avoiding moving a largeamount of data to the processor(s) 1208 for the set membership queries.

For example, the database stored in the memory 1206 of the computedevice 1202 includes a table with a list of names of people, theirresidency information, and their income. The processor 1208 requests theaccelerator 1204 to find how many unique state(s) there are in thedatabase. In response, the accelerator 1204 generates a bit-map outputtable, which is configured to store bit-map output bits for everypossible state of the input data. In other words, the bit-map outputtable includes 50 bit-map output bits to represent 50 states.Subsequently, the accelerator 1204 receives the residency informationcolumn data from the memory 1206, determines the state that each elementor people live in, and sets a bit-map output bit that corresponds toeach state. For example, if a person lives in Indiana, the accelerator1204 sets a bit-map output bit of the bit-map output table thatcorresponds to Indiana to 1. Accordingly, if there are 10 unique statesin the database, meaning that all people live in one of those 10 states,the accelerator 1204 outputs the bit-map output table that includes 10bit-map output bits that have value of 1.

The accelerator 1204 may be embodied as any coprocessor,application-specific integrated circuit (ASIC), field-programmable gatearray (FPGA), a system-on-a-chip (SOC), an application specificintegrated circuit (ASIC), functional block, IP core, or other hardwareaccelerator of the compute device 1202 capable of performing thefunctions described herein. As discussed above, the accelerator 1204 isconfigured to determine unique element values from the database. To doso, as shown in FIG. 12, the accelerator 1204 includes a decompressor1212, an input pre-processing unit 1214, a write request generator unit1216, and an output processing unit 1218. As discussed above, theaccelerator 1204 also includes a definition table 1220 that may bestored in external memory 1222 of the accelerator 1204 and local memory1224 of the accelerator 1204.

The decompressor 1212 may be embodied as any hardware component(s) orcircuitry capable of decompressing the input data. Typically, the inputdata is compressed column data stored in the memory 1206. As such, thedecompressor 1212 may determine whether the input data is compresseddata and decompress the compressed input data in response to determiningthat the input data is compressed.

The input pre-processing unit 1214 may be embodied as any hardwarecomponent(s) or circuitry capable of pre-processing the input data tosupport unique values queries on any bit-width of elements of thedatabase. To do so, the input pre-processing unit 1214 may determine alargest power of 2 elements (i.e., 2^(m) elements) that is to beprocessed in each cycle as a function of an element width of the inputdata and a data path width of the accelerator 1204. The inputpre-processing unit 1214 may align the elements of the uncompressedinput data (e.g., the packed bit vector of column data) and prepend zeroto each element of the input data based on the data path width in orderto process the largest power of 2 elements per cycle. For example, ifthe accelerator 1204 has a 32 bit wide data path, the inputpre-processing unit 1214 may process 32 elements for an element width of1 bit, 16 elements for an element width of 2 bits, 8 elements forelement widths 3 or 4 bits, 4 elements for element widths from 5 to 8bits, and so on.

The write request generator unit 1216 may be embodied as any hardwarecomponent(s) or circuitry capable of generating a write request for eachelement of the input data to set a corresponding bit-map output bit ofthe bit-map output table which corresponds to an element value of thecorresponding element. To do so, the write request generator unit 1216may generate a write request address for the corresponding element toaccess a corresponding bit-map output bit of the bit-map output table.Since the input data is pre-processed, the write request generator unit1216 may extract each element and use the corresponding element value asa write request address to issue a write request to the correspondingbit-map output table. Alternatively, if the hash width (K) is less thanthe element width (N), the write request generator unit 1216 may computea K-bit hash value that corresponds to the element value of thecorresponding element and use the hash value as a write request addressfor the corresponding element to access the bit-map output table. Itshould be appreciated that the hash function may be programmed based onthe element width (N) of the input data and the hash width (K) indicatedin the query configuration data. For example, the write requestgenerator unit 1216 may extract K bits of the N-bit element bytruncating a number of upper and/or lower bits of the N-bit element. Insome embodiments, the hash function may be performed prior topre-processing the input data.

The output processing unit 1218 may be embodied as any hardwarecomponent(s) or circuitry capable of outputting the bit-map outputtable, where each set bit-map output bit of the bit-map output table(e.g., a bit-map output bit that has a value of 1) indicates a presenceof a unique element value corresponds to the bit-map output bit. Theoutput processing unit 1218 may be further configured to accumulate thebit-map output bits until a width of the bit-map output bits reaches thedata path width to transmit the bit-map output bits to the memory 1206for further analysis by one or more processors 1208. In someembodiments, the output processing unit 1218 may directly communicatewith one or more processors 1208 to transmit the bit-map output table.

The processor 1208 may be embodied as any type of processor capable ofperforming the functions described herein. For example, the processor1208 may be embodied as a single or multi-core processor(s), digitalsignal processor, microcontroller, or other processor orprocessing/controlling circuit. Similarly, the memory 1206 may beembodied as any type of volatile or non-volatile memory or data storagecapable of performing the functions described herein. In operation, thememory 1206 may store various data and software used during operation ofthe compute device 1202 such operating systems, applications, programs,libraries, and drivers. The memory 1206 is communicatively coupled tothe processor 1208 via the input/output (I/O) subsystem (not shown),which may be embodied as circuitry and/or components to facilitateinput/output operations with the processor 1208, the accelerator 1204,the memory 1206, the one or more storage devices 1210, and othercomponents of the compute device 1202. For example, the I/O subsystemmay be embodied as, or otherwise include, memory controller hubs,input/output control hubs, sensor hubs, firmware devices, communicationlinks (i.e., point-to-point links, bus links, wires, cables, lightguides, printed circuit board traces, etc.) and/or other components andsubsystems to facilitate the input/output operations. In someembodiments, the I/O subsystem may form a portion of a system-on-a-chip(SoC) and be incorporated, along with the processor 1208, the memory1206, and other components of the compute device 1202, on a singleintegrated circuit chip.

The memory 1206 may be embodied as any type of volatile (e.g., dynamicrandom access memory (DRAM), etc.) or non-volatile memory or datastorage capable of performing the functions described herein. Volatilememory may be a storage medium that requires power to maintain the stateof data stored by the medium. Non-limiting examples of volatile memorymay include various types of random access memory (RAM), such as dynamicrandom access memory (DRAM) or static random access memory (SRAM). Oneparticular type of DRAM that may be used in a memory module issynchronous dynamic random access memory (SDRAM). In particularembodiments, DRAM of a memory component may comply with a standardpromulgated by JEDEC, such as JESD79F for DDR SDRAM, JESD79-2F for DDR2SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 forLow Power DDR (LPDDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, andJESD209-4 for LPDDR4 (these standards are available at www.jedec.org).Such standards (and similar standards) may be referred to as DDR-basedstandards and communication interfaces of the storage devices thatimplement such standards may be referred to as DDR-based interfaces.

In one embodiment, the memory device is a block addressable memorydevice, such as those based on NAND or NOR technologies. A memory devicemay also include future generation nonvolatile devices, such as a threedimensional crosspoint memory device (e.g., Intel 3D XPoint™ memory), orother byte addressable write-in-place nonvolatile memory devices. In oneembodiment, the memory device may be or may include memory devices thatuse chalcogenide glass, multi-threshold level NAND flash memory, NORflash memory, single or multi-level Phase Change Memory (PCM), aresistive memory, nanowire memory, ferroelectric transistor randomaccess memory (FeTRAM), anti-ferroelectric memory, magnetoresistiverandom access memory (MRAM) memory that incorporates memristortechnology, resistive memory including the metal oxide base, the oxygenvacancy base and the conductive bridge Random Access Memory (CB-RAM), orspin transfer torque (STT)-MRAM, a spintronic magnetic junction memorybased device, a magnetic tunneling junction (MTJ) based device, a DW(Domain Wall) and SOT (Spin Orbit Transfer) based device, a thyristorbased memory device, or a combination of any of the above, or othermemory. The memory device may refer to the die itself and/or to apackaged memory product.

In some embodiments, 3D crosspoint memory (e.g., Intel 3D XPoint™memory) may comprise a transistor-less stackable cross pointarchitecture in which memory cells sit at the intersection of word linesand bit lines and are individually addressable and in which bit storageis based on a change in bulk resistance. In some embodiments, all or aportion of the memory 1206 may be integrated into the processor 1208. Inoperation, the memory 1206 may store various software and data usedduring operation such as resource utilization data, resourceavailability data, application programming interface (API) data,applications, programs, and libraries.

The illustrative storage devices 1210 may be embodied as any type ofdevices configured for short-term or long-term storage of data such as,for example, memory devices and circuits, memory cards, hard diskdrives, solid-state drives, or other data storage devices. Each storagedevice 1210 may include a system partition that stores data and firmwarecode for the storage device 1210. Each storage device 1210 may alsoinclude one or more operating system partitions that store data filesand executables for operating systems.

Although illustrated in FIG. 12 as a single compute device 1202, itshould be understood that in some embodiments the functions of thecompute device 1202 may be performed by one or more sleds in a datacenter. In such embodiments, the accelerator 1204 may be embodied as oneor more accelerator sled 204-2 (e.g., physical accelerator resources205-2), the memory 1206 may be embodied as one or more memory sled 204-3(e.g., physical memory resources 205-3), one or more processors 1208 maybe embodied as one or more compute sled 204-4 (e.g., physical computeresources 205-4), one or more storage devices 1210 may be embodied asone or more storage sleds 204-1 (e.g., physical storage resources205-1).

Referring now to FIG. 13, in the illustrative embodiment, theaccelerator 1204 of the compute device 1202 may establish an environment1300 during operation. In the illustrative embodiment, the environment1300 includes a large bit-map output table 1340 and a small bit-mapoutput table 1350. The large bit-map output table 1340 may be embodiedas any data indicative of bit-map output bits for elements that have abit-width greater than a predefined number of bit-width. Whereas, thesmall bit-map output table 1350 may be embodied as any data indicativeof bit-map output bits for elements that have a bit-width smaller thanthe predefined number of bit-width. As discussed above, each bit-mapoutput bit that is set indicates a presence of unique element value. Itshould be appreciated that, in the embodiment where the hash width (K)is less than the element width (N), each bit-map output bit that is setindicates a presence of a hash value, which corresponds to a uniqueelement value. Additionally, the illustrative environment 1300 includesan input/output (I/O) communicator 1310, a decompressor 1320, andcomplex filter 1330. The complex filter 1330 further includes a bit-maptable generator 1332, an input data pre-processor 1334, a write requestgenerator 1336, and a bit-map output generator 1338. Each of thecomponents of the environment 1300 may be embodied as hardware,firmware, software, or a combination thereof. As such, in someembodiments, one or more of the components of the environment 1300 maybe embodied as circuitry or a collection of electrical devices (e.g.,I/O communicator circuitry 1310, decompressor circuitry 1320, complexfilter circuitry 1330, bit-map table generator circuitry 1332, inputdata pre-processor circuitry 1334, write request generator circuitry1336, bit-map output generator circuitry 1338, etc.).

In the illustrative environment 1300, the I/O communicator 1310 isconfigured to facilitate inbound and outbound network communications(e.g., network traffic, network packets, network flows, etc.) to andfrom the accelerator 1204, respectively. To do so, the I/O communicator1310 is configured to receive and process data from the memory 1206based on unique values queries received from a processor 1208 of thecompute device 1202. The I/O communicator 1310 is further configured totransmit a bit-map output data to the memory 1206. In some embodiments,the accelerator 1204 may receive from or transmit to one or more storagedevices 1210. Accordingly, in some embodiments, at least a portion ofthe functionality of the I/O communicator 1310 may be performed bycommunication circuitry of the compute device 1202.

The decompressor 1320, which may be embodied as hardware, firmware,software, virtualized hardware, emulated architecture, and/or acombination thereof as discussed above, is configured to decompress theinput data. The decompressor 1212 is configured to determine whether theinput data is compressed data and decompress the compressed input datain response to determining that the input data is compressed.

The complex filter 1330, which may be embodied as hardware, firmware,software, virtualized hardware, emulated architecture, and/or acombination thereof as discussed above, is configured to filter theinput data to determine unique element values of the input data. To doso, the complex filter 1330 includes the bit-map table generator 1332,the input data pre-processor 1334, the write request generator 1336, andthe bit-map output generator 1338.

The bit-map table generator 1332 is configured to generate a bit-mapoutput table. As described above, the bit-map output table is configuredto store bit-map output bits, where each bit-map output bit correspondsto a unique element value or hash value of the input data. As such, thebit-map output table has 2^(K) number of bit-map output bits torepresent 2^(K) unique element values. In the illustrative embodiment,the bit-map table generator 1332 is configured to construct a differenttype of definition table (e.g., a small or large bit-map output table)on the accelerator 1240 based on the hash width (K). If the bit-maptable generator 1332 determines that the hash width (K) is less than apredefined width, the bit-map table generator 1332 constructs a smallbit-map output table that has many write ports as necessary to satisfy atarget throughput based on the width of the data path of the accelerator1204. For example, if the hash width (K) is less than 8 bits, thebit-map output bits are stored in a small bit-map output table withmultiple write ports to provide multiple writes per cycle. To generate abit-map output table that supports elements up to 8 bits, the bit-maptable generator 1332 implements 256 flip flops to construct a smallbit-map output table. In this example, if the width of the data path ofthe accelerator 1204 is 32 bit, the bit-map table generator 1332constructs the small bit-map output table with 2 flip flops for 32 writeports of a 1 bit element (e.g., 2:1 multiplexers), 4 flip flops for 16write ports of a 2 bit element (e.g., 4:1 multiplexers), 16 flip flopsfor 8 write ports of a 3 or 4 bit element (e.g., 16:1 multiplexers), andremaining flip flops for 4 write ports. Alternatively, if the hash width(K) is greater than 8 bits, the bit-map output bits are stored in alarge bit-map output table. The accelerator 1204 may configure the largebit-map output table to store duplicate copies of the bit-map outputbits to support parallel accesses. It should be appreciated that, insome embodiments, the accelerator 1204 may also configure the smallbit-map output table to store multiple copies of the bit-map output bitsto support multiple accesses.

The input data pre-processor 1334 is configured to pre-process the inputdata to support unique element values queries on any bit-width ofelements of the database. To do so, the input data pre-processor 1334 isconfigured to determine a largest power of 2 elements (i.e., 2^(m)elements) that is to be processed in each cycle as a function of anelement width of the input data and a data path width of the accelerator1204. The input data pre-processor 1334 is further configured to alignthe elements of the uncompressed input data (i.e., the packed bit vectorof column data) and prepend zero to each element of the input data basedon the data path width in order to process the largest power of 2elements per cycle. For example, if the accelerator 1204 has a 32 bitwide data path, the input data pre-processor 1334 may process 32elements for element with 1 bit, 16 elements for element width of 2bits, 8 elements for element widths 3 or 4 bits, or 4 elements forelement widths from 5 to 8 bits, and so on.

The write request generator 1336 is configured to generate a writerequest for each element of the input data to access the correspondingbit-map output table to set a corresponding bit-map output bit of thebit-map output table. To do so, the accelerator 1204 may generate awrite request address for the corresponding element to access thebit-map output table. Since the input data is pre-processed and alignedwith the bit-map output table, if the element width (N) and the hashwidth (K) are the same, the accelerator 1204 may extract each elementand use the corresponding element value as a write request address toissue a write request to the corresponding bit-map output table.However, if the element width (N) is different than the hash width (K),the accelerator 1204 may extract each element and use a correspondinghash value as a write request address to issue a write request to thecorresponding bit-map output table. To do so, the accelerator 1204 isconfigured to generate a hash value that corresponds to each elementvalue for every element of the input data using a hash function that isconfigured based the element width (N) and the hash width (N).

The bit-map output generator 1338 is configured to output the bit-mapoutput table that indicates unique element values that are present inthe input data. As described above, in some embodiments, the bit-mapoutput table may include duplicate copies of the bit-map output tosupport parallel accesses by mimicking multiple write ported memory. Insuch embodiments, the bit-map output generator 1338 may combine thecorresponding bits from each copy of the bit-map output by using alogical OR operation to generate the true bit-map output bit of thebit-map output table. It should be appreciated that each bit-map outputbit of the bit-map output table that has been set indicates a presenceof a unique element value that corresponds to the bit-map output bit. Assuch, the bit-map output generator 1338 may be configured to determine atotal number of unique element values that are present in the input databy adding a number of bit-map output bits that have been set. Thebit-map output generator 1338 may be further configured to accumulatethe bit-map output bit data until a width of the bit-map output reachesthe data path width and transmit the bit-map output bit data to thememory 1206 for further analysis or processing by one or more processors1208. In some embodiments, the bit-map output generator 1338 maydirectly communicate with one or more processors 1208 to transmit thebit-map output bit table.

Referring now to FIGS. 14 and 15, in use, the accelerator 1204 of thecompute device 1202 may execute a method 1400 for determining uniqueelement values. The method 1400 begins with block 1402, in which theaccelerator 1204 imports input data from the memory 1206 of the computedevice 1202. Typically, the input data is compressed data stored in thememory 1206. As such, the accelerator 1204 decompresses the compressedinput data as indicated in block 1404.

In block 1406, the accelerator 1204 receives query configuration datafrom a requesting processor 1208 of the compute device 1202. Forexample, the accelerator 1204 may receive from the processor 1208 apointer to query configuration data in the memory 1206. However, itshould be appreciated that, in some embodiments, the query configurationdata may be received from other components of the compute device 1202.As described above, the query configuration data may include a number ofelements and an element width (N) of the input data and a hash width(K). Accordingly, in block 1408, the accelerator 1204 determines anumber elements and an element width (N) of the input data. In someembodiments, in block 1410 the accelerator 1204 may determine a hashwidth (K) if the element width (N) of the input data is different fromthe hash width (K). Additionally, in block 1412, the accelerator 1204determines a number of elements to be processed per cycle based on theelement width (N) and a data path width of the accelerator 1204.

Subsequently, the accelerator 1204 constructs a bit-map output tablethat is configured to store bit-map output bits. The bit-map output bitsrepresent all possible element values of the input data, such that eachbit-map output bit represents a unique element value of the input data.Accordingly, the bit-map output table includes two to the hash width (K)power number of bit-map output bits. For example, the bit-map outputbits for a 8-bit hash width includes 2⁸ or 256 bits, the bit-map outputbits for a 32-bit hash width includes 2³² bits or 512 MB, and so on. Itshould be appreciated that, in the illustrative embodiment, all bit-mapoutput bits stored in the bit-map output table are initially cleared(e.g., a default value of 0).

As described above, the accelerator 1240 configures a different bit-mapoutput table on the accelerator 1240 based on the hash width (K). To doso, in block 1414, the accelerator 1204 determines whether the hashwidth (K) is greater than a predefined width. If the accelerator 1204determines that the hash width (K) is smaller than the predefinedthreshold of element width, the method 1400 advances to block 1416. Inblock 1416, the accelerator 1204 constructs a small bit-map output tableto store the bit-map output bits. The small bit-map output table is tosupport multiple write ports to provide multiple writes per cycle asindicated in block 1418. For example, if the element width is less than8 bits, the bit-map output bits are stored in a small bit-map outputtable with multiple write ports to provide multiple writes per cycle.

Alternatively, if the accelerator 1204 determines that the hash width(K) is greater than the predefined threshold width in block 1414, themethod 1400 advances to block 1420. In block 1420, the accelerator 1204constructs a large bit-map output table to store the bit-map outputbits. Although multiple write ports may be implemented to construct asmall bit-map output table for processing data having a small elementwidth, implementing multiple write ports for a large data having a largeelement width may be impractical and costly. As such, the accelerator1204 may store duplicate copies of the bit-map output bits to supportparallel accesses per cycle as indicated in block 1422. To do so, thebit-map output bits are stored in different banks such that eachmembership bit vector in each bank is accessed simultaneously, therebysupporting parallel accesses. For example, if the width of each elementis greater than 8 bits, the accelerator 1204 may configure a largebit-map output table to store duplicate copies of the bit-map outputbits to support parallel accesses.

Subsequent to constructing the bit-map output table, in block 1424, theaccelerator 1204 determines whether the element width (N) equals to thehash width (K). If the accelerator 1204 determines that the elementwidth (N) and the hash width (K) are the same, the method 1400 skipsahead to block 1428 shown in FIG. 15. If, however, the accelerator 1204determines that the element width (N) is different than the hash width(K), the method 1400 advances to block 1426, in which the accelerator1204 programs a hash function that is configured to generate a K-bithash value from a N-bit element value for every elements of the inputdata.

Subsequently, in block 1428 shown in FIG. 15, the accelerator 1204pre-processes the input data to prepare the elements of the input datafor the unique element value function. To do so, the accelerator 1204may align the elements of the input data (i.e., the packed array ofunsigned integers of column data) based on the number of elements thatis to be processed in each cycle as indicated in block 1430. Asdescribed above, the number of elements that is to be processed in eachcycle is determined based on the element width (N) of the input data anda data path width of the accelerator 1204. Additionally, in block 1432the accelerator 1204 may prepend zeros to each element of the input databased on the data path width in order to process a largest power of 2elements per cycle (i.e., largest 2^(m) elements/cycle). For example, ifthe accelerator 1204 has a 32 bit wide data path, the accelerator 1204may process 32 elements for element with 1 bit, 16 elements for elementwidth of 2 bits, 8 elements for element widths 3 or 4 bits, or 4elements for element widths from 5 to 8 bits, and so on.

In block 1434, the accelerator 1204 generates a write request for eachelement of the input data to access the corresponding bit-map outputtable to set a corresponding bit-map output bit of the bit-map outputtable. To do so, the accelerator 1204 may generate a write requestaddress for the corresponding element to access the bit-map outputtable. Since the input data is pre-processed and aligned with thebit-map output table, if the element width (N) and the hash width (K)are the same, the accelerator 1204 may extract each element and use thecorresponding element value as a write request address to issue a writerequest to the corresponding bit-map output table as indicated in block1436. However, if the element width (N) is different than the hash width(K), the accelerator 1204 may use a corresponding hash value as a writerequest address to issue a write request to the corresponding bit-mapoutput table as indicated in block 1438. To do so, in block 1440, theaccelerator 1204 generates a hash value that corresponds to each elementvalue for every element of the input data. In block 1442, the writerequest is transmitted to the corresponding bit-map output table. Inresponse to generating the write requests for each element of the inputdata, in block 1444, the accelerator 1204 accesses the correspondingbit-map output table to set the corresponding bit-map output bits basedon the write requests.

Subsequently, in block 1446, the accelerator 1204 output the bit-mapoutput table that includes the bit-map output bits indicating uniqueelement values that are present in the input data. As discussed above,each output bit of the bit-map output table that has been setcorresponds to a presence of a unique element value. As such, in someembodiments, a total number of unique elements present in the input datamay be determined by generating a population count by adding a number ofbit-map output bits that have been set as indicated in block 1448. Insome embodiments, in block 1450, the accelerator 1204 may accumulate thebit-map output table data until a width of the bit-map output table datareaches the data path width of the accelerator and transmit the bit-mapoutput table to the memory 1206 for further processing by one or moreprocessors 1208. In some embodiments, the bit-map output table may bedirectly transmitted to the processor 1208.

EXAMPLES

Illustrative examples of the technologies disclosed herein are providedbelow. An embodiment of the technologies may include any one or more,and any combination of, the examples described below.

Example 1 includes a compute device for determining unique values, thecompute device comprising one or more accelerator devices, eachaccelerator device is to receive input data and query configurationdata, the input data including a packed array of unsigned integers ofcolumn data from a database and the query configuration data includingan element width of the input data; generate, in response to receivingthe query configuration data, a bit-map output table based on the queryconfiguration data; generate a write request for each element of theinput data to set a corresponding bit-map output bit of the bit-mapoutput table which corresponds to an element value of the correspondingelement; set the corresponding bit-map output bit to indicate a presenceof the corresponding element in response to generation of the writerequest; and output the bit-map output table indicative of uniqueelements that are present in the input data in response to setting ofthe corresponding bit-map output bit.

Example 2 includes the subject matter of Example 1, and wherein the eachaccelerator is further to decompress, in response to importation of theinput data, the input data; and pre-process, in response todecompression of the input data, the decompressed input data.

Example 3 includes the subject matter of any of Examples 1 and 2, andwherein to pre-process the decompressed input data comprises to alignelements of the packed bit vector of the input data based on a width ofelements of the decompressed input data and prepend zeroes to match adata path width.

Example 4 includes the subject matter of any of Examples 1-3, andwherein the query configuration data further includes a hash width.

Example 5 includes the subject matter of any of Examples 1-4, andwherein the each accelerator is further to determine whether the elementwidth is greater than the hash width; program, in response to adetermination that the element width is greater than the hash width, ahash function to generate a hash value that corresponds to the elementvalue of the corresponding element; and generate, in response toprogramming of the hash function, a hash value for each element value byperforming the hash function on the input data.

Example 6 includes the subject matter of any of Examples 1-5, andwherein to generate the write request comprises to generate a writerequest address based on a hash value of the corresponding element.

Example 7 includes the subject matter of any of Examples 1-6, andwherein to generate the write request comprises to determine a writerequest address based on an element value of the corresponding element.

Example 8 includes the subject matter of any of Examples 1-7, andwherein to generate the bit-map output table based on the queryconfiguration data comprises to determine whether the element width ofthe input data exceeds a threshold; construct, in response to adetermination that the element width exceeds the threshold, a largebit-map output table to store the bit-map output bits; and construct, inresponse to a determination that the element width does not exceed thethreshold, a small bit-map output table to store the bit-map outputbits.

Example 9 includes the subject matter of any of Examples 1-8, andwherein the large bit-map output table supports parallel accesses byduplication of the bit-map output table and the small-sized tablesupports multiple accesses via multiple write ports and duplication ofthe bit-map output table.

Example 10 includes the subject matter of any of Examples 1-9, andwherein to set the corresponding bit-map output bit comprises todetermine whether the element width exceeds a threshold; access, inresponse to a determination that the element width exceeds thethreshold, the large bit-map output table to set the correspondingbit-map output bit; and access, in response to a determination that theelement width does not exceed the threshold, the small bit-map outputtable to set the corresponding bit-map output bit.

Example 11 includes the subject matter of any of Examples 1-10, andwherein to output the bit-map output table comprises to generate apopulation count indicating a number of unique elements based on thebit-map output table.

Example 12 includes the subject matter of any of Examples 1-11, andwherein the each accelerator is further to accumulate the bit-map outputtable until a width of the bit-map output table matches a data pathwidth.

Example 13 includes a method for determining unique values by a computedevice, the method comprising receiving, by an accelerator of thecompute device, input data and query configuration data, the input dataincluding a packed array of unsigned integers of column data from adatabase and the query configuration data including an element width ofthe input data; generating, in response to receiving the queryconfiguration data and by the accelerator, a bit-map output table basedon the query configuration data; generating, by the accelerator, a writerequest for each element of the input data to set a correspondingbit-map output bit of the bit-map output table which corresponds to anelement value of the corresponding element; setting, by the accelerator,the corresponding bit-map output bit to indicate a presence of thecorresponding element in response to generating the write request; andoutputting, by the accelerator, the bit-map output table indicative ofunique elements that are present in the input data in response tosetting the corresponding bit-map output bit.

Example 14 includes the subject matter of Example 13, and furtherincluding decompressing, in response to importing the input data and bythe accelerator, the input data; and pre-processing, in response todecompressing the input data and by the accelerator, the decompressedinput data.

Example 15 includes the subject matter of any of Examples 13 and 14, andwherein pre-processing the decompressed input data comprises aligning,by the accelerator, elements of the packed bit vector of the input databased on a width of elements of the decompressed input data andprepending, by the accelerator, zeroes to match a data path width.

Example 16 includes the subject matter of any of Examples 13-15, andwherein the query configuration data further includes a hash width.

Example 17 includes the subject matter of any of Examples 13-16, andfurther including determining, by the accelerator, whether the elementwidth is greater than the hash width; programming, in response to adetermination that the element width is greater than the hash width andby the accelerator, a hash function to generate a hash value thatcorresponds to the element value of the corresponding element; andgenerating, in response to programming the hash function and by theaccelerator, a hash value for each element value by performing the hashfunction on the input data.

Example 18 includes the subject matter of any of Examples 13-17, andwherein generating the write comprises determining, by the accelerator,a write request address based on a hash value of the correspondingelement.

Example 19 includes the subject matter of any of Examples 13-18, andwherein generating the write comprises determining, by the accelerator,a write request address based on an element value of the correspondingelement.

Example 20 includes the subject matter of any of Examples 13-19, andwherein generating the bit-map output table based on the queryconfiguration data comprises determining, by the accelerator, whetherthe element width of the input data exceeds a threshold; constructing,in response to a determination that the element width exceeds thethreshold, a large bit-map output table to store the bit-map outputbits; and constructing, in response to a determination that the elementwidth does not exceed the threshold, a small bit-map output table tostore the bit-map output bits.

Example 21 includes the subject matter of any of Examples 13-20, andwherein the large bit-map output table supports parallel accesses byduplicating the bit-map output table and the small-sized table supportsmultiple accesses via multiple write ports and duplicating the bit-mapoutput table.

Example 22 includes the subject matter of any of Examples 13-21, andwherein setting the corresponding bit-map output bit comprisesdetermining, by the accelerator, whether the element width exceeds athreshold; accessing, in response to a determination that the elementwidth exceeds the threshold and by the accelerator, the large bit-mapoutput table to set the corresponding bit-map output bit; and accessing,in response to a determination that the element width does not exceedthe threshold and by the accelerator, the small bit-map output table toset the corresponding bit-map output bit.

Example 23 includes the subject matter of any of Examples 13-22, andwherein outputting the bit-map output table comprises generating, by theaccelerator, a population count indicating a number of unique elementsbased on the bit-map output table.

Example 24 includes the subject matter of any of Examples 13-23, andfurther including accumulating, by the accelerator, the bit-map outputtable until a width of the bit-map output table matches a data pathwidth.

Example 25 includes a compute device comprising means for performing themethod of any of Examples 13-24.

Example 26 includes one or more machine-readable storage mediacomprising a plurality of instructions stored thereon that, in responseto being executed, cause a compute device to perform the method of anyof Examples 13-24.

Example 27 includes a compute device comprising a compute engine toperform the method of any of Examples 13-24.

Example 28 includes a compute device for determining unique values, thecompute device comprising one or more accelerator devices, eachaccelerator device comprising means for receiving input data and queryconfiguration data, the input data including a packed array of unsignedintegers of column data from a database and the query configuration dataincluding an element width of the input data; means for generating, inresponse to receiving the query configuration data, a bit-map outputtable based on the query configuration data; means for generating awrite request for each element of the input data to set a correspondingbit-map output bit of the bit-map output table which corresponds to anelement value of the corresponding element; means for setting thecorresponding bit-map output bit to indicate a presence of thecorresponding element in response to generating the write request; andmeans for outputting the bit-map output table indicative of uniqueelements that are present in the input data in response to setting thecorresponding bit-map output bit.

Example 29 includes the subject matter of Example 28, and wherein theeach accelerator device further comprises means for decompressing, inresponse to importing the input data, the input data; and means forpre-processing, in response to decompressing the input data, thedecompressed input data.

Example 30 includes the subject matter of any of Examples 28 and 29, andwherein the means for pre-processing the decompressed input datacomprises means for aligning elements of the packed bit vector of theinput data based on a width of elements of the decompressed input dataand means for prepending zeroes to match a data path width.

Example 31 includes the subject matter of any of Examples 28-30, andwherein the query configuration data further includes a hash width.

Example 32 includes the subject matter of any of Examples 28-31, andwherein the each accelerator further comprises means for determiningwhether the element width is greater than the hash width; means forprogramming, in response to a determination that the element width isgreater than the hash width, a hash function to generate a hash valuethat corresponds to the element value of the corresponding element; andmeans for generating, in response to programming the hash function, ahash value for each element value by performing the hash function on theinput data.

Example 33 includes the subject matter of any of Examples 28-32, andwherein the means for generating the write comprises means fordetermining a write request address based on a hash value of thecorresponding element.

Example 34 includes the subject matter of any of Examples 28-33, andwherein the means for generating the write comprises means fordetermining a write request address based on an element value of thecorresponding element.

Example 35 includes the subject matter of any of Examples 28-34, andwherein the means for generating the bit-map output table based on thequery configuration data comprises means for determining whether theelement width of the input data exceeds a threshold; means forconstructing, in response to a determination that the element widthexceeds the threshold, a large bit-map output table to store the bit-mapoutput bits; and means for constructing, in response to a determinationthat the element width does not exceed the threshold, a small bit-mapoutput table to store the bit-map output bits.

Example 36 includes the subject matter of any of Examples 28-35, andwherein the large bit-map output table supports parallel accesses byduplicating the bit-map output table and the small-sized table supportsmultiple accesses via multiple write ports and duplicating the bit-mapoutput table.

Example 37 includes the subject matter of any of Examples 28-36, andwherein the means for setting the corresponding bit-map output bitcomprises means for determining whether the element width exceeds athreshold; means for accessing, in response to a determination that theelement width exceeds the threshold, the large bit-map output table toset the corresponding bit-map output bit; and means for accessing, inresponse to a determination that the element width does not exceed thethreshold, the small bit-map output table to set the correspondingbit-map output bit.

Example 38 includes the subject matter of any of Examples 28-37, andwherein the means for outputting the bit-map output table comprisesmeans for generating a population count indicating a number of uniqueelements based on the bit-map output table.

Example 39 includes the subject matter of any of Examples 28-38, andwherein the each accelerator further comprises means for accumulatingthe bit-map output table until a width of the bit-map output tablematches a data path width.

1. A computing device for determining unique values, the computingdevice comprising one or more accelerator devices, each acceleratordevice is to: receive input data and query configuration data, the inputdata including a packed array of unsigned integers of column data from adatabase and the query configuration data including an element width ofthe input data; generate, in response to receiving the queryconfiguration data, a bit-map output table based on the queryconfiguration data; generate a write request for each element of theinput data to set a corresponding bit-map output bit of the bit-mapoutput table which corresponds to an element value of the correspondingelement; set the corresponding bit-map output bit to indicate a presenceof the corresponding element in response to generation of the writerequest; and output the bit-map output table indicative of uniqueelements that are present in the input data in response to setting ofthe corresponding bit-map output bit.
 2. The computing device of claim1, wherein the each accelerator is further to: decompress, in responseto importation of the input data, the input data; and pre-process, inresponse to decompression of the input data, the decompressed inputdata.
 3. The computing device of claim 2, wherein to pre-process thedecompressed input data comprises to align elements of the packed bitvector of the input data based on a width of elements of thedecompressed input data and prepend zeroes to match a data path width.4. The computing device of claim 1, wherein the query configuration datafurther includes a hash width.
 5. The computing device of claim 4,wherein the each accelerator is further to: determine whether theelement width is greater than the hash width; program, in response to adetermination that the element width is greater than the hash width, ahash function to generate a hash value that corresponds to the elementvalue of the corresponding element; and generate, in response toprogramming of the hash function, a hash value for each element value byperforming the hash function on the input data.
 6. The computing deviceof claim 4, wherein to generate the write request comprises to generatea write request address based on a hash value of the correspondingelement.
 7. The computing device of claim 1, wherein to generate thewrite request comprises to determine a write request address based on anelement value of the corresponding element.
 8. The computing device ofclaim 1, wherein to generate the bit-map output table based on the queryconfiguration data comprises to: determine whether the element width ofthe input data exceeds a threshold; construct, in response to adetermination that the element width exceeds the threshold, a largebit-map output table to store the bit-map output bits; and construct, inresponse to a determination that the element width does not exceed thethreshold, a small bit-map output table to store the bit-map outputbits.
 9. The computing device of claim 8, wherein the large bit-mapoutput table supports parallel accesses by duplication of the bit-mapoutput table and the small-sized table supports multiple accesses viamultiple write ports and duplication of the bit-map output table. 10.The computing device of claim 8, wherein to set the correspondingbit-map output bit comprises to: determine whether the element widthexceeds a threshold; access, in response to a determination that theelement width exceeds the threshold, the large bit-map output table toset the corresponding bit-map output bit; and access, in response to adetermination that the element width does not exceed the threshold, thesmall bit-map output table to set the corresponding bit-map output bit.11. The computing device of claim 10, wherein to output the bit-mapoutput table comprises to generate a population count indicating anumber of unique elements based on the bit-map output table.
 12. Thecomputing device of claim 10, wherein the each accelerator is further toaccumulate the bit-map output table until a width of the bit-map outputtable matches a data path width.
 13. One or more machine-readablestorage media comprising a plurality of instructions stored thereonthat, when executed by a compute device cause an accelerator of thecompute device to: receive input data and query configuration data, theinput data including a packed array of unsigned integers of column datafrom a database and the query configuration data including an elementwidth of the input data; generate, in response to receiving the queryconfiguration data, a bit-map output table based on the queryconfiguration data; generate a write request for each element of theinput data to set a corresponding bit-map output bit of the bit-mapoutput table which corresponds to an element value of the correspondingelement; set the corresponding bit-map output bit to indicate a presenceof the corresponding element in response to generation of the writerequest; and output the bit-map output table indicative of uniqueelements that are present in the input data in response to setting ofthe corresponding bit-map output bit.
 14. The one or moremachine-readable storage media of claim 13, further comprising aplurality of instructions stored thereon that, in response to beingexecuted, cause the accelerator of the compute device to: decompress, inresponse to importation of the input data, the input data; andpre-process, in response to decompression of the input data, thedecompressed input data.
 15. The one or more machine-readable storagemedia of claim 14, wherein to pre-process the decompressed input datacomprises to align elements of the packed bit vector of the input databased on a width of elements of the decompressed input data and prependzeroes to match a data path width.
 16. The one or more machine-readablestorage media of claim 13, further comprising a plurality ofinstructions stored thereon that, in response to being executed, causethe accelerator of the compute device to: determine whether the elementwidth is greater than a hash width, wherein the hash width is includedin the query configuration data; program, in response to a determinationthat the element width is greater than the hash width, a hash functionto generate a hash value that corresponds to the element value of thecorresponding element; and generate, in response to programming of thehash function, a hash value for each element value by performing thehash function on the input data.
 17. The one or more machine-readablestorage media of claim 13, wherein to generate the bit-map output tablebased on the query configuration data comprises to: determine whetherthe element width of the input data exceeds a threshold; construct, inresponse to a determination that the element width exceeds thethreshold, a large bit-map output table to store the bit-map outputbits; and construct, in response to a determination that the elementwidth does not exceed the threshold, a small bit-map output table tostore the bit-map output bits.
 18. The one or more machine-readablestorage media of claim 17, wherein the large bit-map output tablesupports parallel accesses by duplication of the bit-map output tableand the small-sized table supports multiple accesses via multiple writeports and duplication of the bit-map output table.
 19. The one or moremachine-readable storage media of claim 17, wherein to set thecorresponding bit-map output bit comprises to: determine whether theelement width exceeds a threshold; access, in response to adetermination that the element width exceeds the threshold, the largebit-map output table to set the corresponding bit-map output bit; andaccess, in response to a determination that the element width does notexceed the threshold, the small bit-map output table to set thecorresponding bit-map output bit.
 20. A method for determining uniquevalues by a computing device, the method comprising: receiving, by anaccelerator of the computing device, input data and query configurationdata, the input data including a packed array of unsigned integers ofcolumn data from a database and the query configuration data includingan element width of the input data; generating, in response to receivingthe query configuration data and by the accelerator, a bit-map outputtable based on the query configuration data; generating, by theaccelerator, a write request for each element of the input data to set acorresponding bit-map output bit of the bit-map output table whichcorresponds to an element value of the corresponding element; setting,by the accelerator, the corresponding bit-map output bit to indicate apresence of the corresponding element in response to generating thewrite request; and outputting, by the accelerator, the bit-map outputtable indicative of unique elements that are present in the input datain response to setting the corresponding bit-map output bit.
 21. Themethod of claim 20 further comprising: decompressing, in response toimporting the input data and by the accelerator, the input data; andpre-processing, in response to decompressing the input data and by theaccelerator, the decompressed input data.
 22. The method of claim 20further comprising: determining, by the accelerator, whether the elementwidth is greater than a hash width, wherein the hash width is includedin the query configuration data; programming, in response to adetermination that the element width is greater than the hash width andby the accelerator, a hash function to generate a hash value thatcorresponds to the element value of the corresponding element; andgenerating, in response to programming the hash function and by theaccelerator, a hash value for each element value by performing the hashfunction on the input data.
 23. The method of claim 13, whereingenerating the bit-map output table based on the query configurationdata comprises: determining, by the accelerator, whether the elementwidth of the input data exceeds a threshold; constructing, in responseto a determination that the element width exceeds the threshold, a largebit-map output table to store the bit-map output bits; and constructing,in response to a determination that the element width does not exceedthe threshold, a small bit-map output table to store the bit-map outputbits.
 24. The method of claim 23, wherein the large bit-map output tablesupports parallel accesses by duplicating the bit-map output table andthe small-sized table supports multiple accesses via multiple writeports and duplicating the bit-map output table.
 25. The method of claim23, wherein setting the corresponding bit-map output bit comprises:determining, by the accelerator, whether the element width exceeds athreshold; accessing, in response to a determination that the elementwidth exceeds the threshold and by the accelerator, the large bit-mapoutput table to set the corresponding bit-map output bit; and accessing,in response to a determination that the element width does not exceedthe threshold and by the accelerator, the small bit-map output table toset the corresponding bit-map output bit.